1. Field of the Invention
The present invention relates in general to a method for bypassing null-code sections in read-only memories (ROM). In particular, the present invention provides a method for bypassing unused storage sections in ROM devices by cutting off the entire access current flow path in the access lines of the ROM device. More particularly, the present invention relates to a method for bypassing the null storage sections while providing correct access results in case these unused null codes are accessed in the device quality control testing, even if defects exist in these null code sections of the ROM device.
2. Description of Related Art
Read-only memory (ROM) is a type of semiconductor storage device that is widely used in various applications. ROM integrated circuits (IC's) are different from other categories of re-writable semiconductor memories, for example, static random access memories (SRAM), dynamic random access memories (DRAM), as well as electronically erasable-programmable read-only memories (E.sup.2 ROM). As their name implies, ROM's are read only, data contained in a ROM IC, either program code or data as provided by a customer of the ROM IC, is normally programmed into the ROM device in a factory. Information contained in the ROM IC can only be read, no new data can be written into the device once after the ROM IC is programmed during its manufacture.
The data to be programmed into the memory array of a ROM IC device, either program code or information, as is well known in the art, is normally converted into a set of binary code represented by a string of 0's and 1's, i.e., bits. These bits are to be stored permanently in the array of memory cells of the ROM IC device. The memory cells in the array are identified and accessible, that is, readable, via an addressing system. For example, in an industry standard one mega-bit ROM device organized as 128K address locations of 8-bit bytes, each of the data bytes comprising either the 0's or 1's to be stored is assigned into the corresponding 8-bit memory locations addressed by the addressing system of the ROM device.
The fabrication process stages for all ROM devices, whether or not they contain the same contents, are the same before the procedure of code programming is performed. In fact, even the code programming phase of fabrication can be considered to be the same for all ROM devices. The only difference being the code contents reflected by different programming masks.
The storage capacity of ROM IC devices is expanding with each generation of device. The capacity expansion is typically doubled once the fabrication technology allows the device to be made with finer resolution. The doubling of the storage capacity is reflecting the fact that expansion of the storage capacity requires the addition of the memory address bits. A minimum increase of one address bit to the device doubles the addressing range of the device. Thus, commercial ROM IC's are available in storage capacities such as 256K, 512K, 1M, 2M, 4M, 8M and 16M bits etc. Capacities smaller than 256K were and still are available, and capacities larger than 16M bits are doubtlessly going to be commercially available as semiconductor technology advances.
With the advent of the these large capacity ROM IC devices, it is frequently the case that nearly one half of the storage capacity is useless for a code storage application. For example, if a program has a code size slightly larger than 1M bits that can not be fitted into a 1M device, then nearly one million bits of storage space in the 2M device will be wasted. Further, typical program codes and data frequently include scattered sections in the entire ROM memory array that contain continuous 0's or 1's. When expressed in ROM IC content listing, consecutive 0's such as 00h for 8-bit devices and 0000h for 16-bit devices observed. On other occasions, these null contents are listed as FFh or FFFFh respectively. The letter "h" indicates that the numbers are in hexadecimal format. In the context of the present invention, these sections of null ROM code will be the sections of storage contents to be "bypassed".
FIG. 1 schematically shows the layout of a block diagram of a conventional semiconductor ROM IC device. In this typical ROM device, memory cells, herein designated as MC, each constructed around a MOS transistor, are arranged in an array of rows and columns. Typically, all the memory bits in the memory word accessed by the same address assignment are assigned into the columns in the memory array, and all the accessible address locations are assigned into the rows. For example, in the 1M device organized as 128K positions of 8-bit bytes, there is a memory array organized as 128K rows by eight columns.
Memory cells MC in the same row have the gates of their respective MOS transistors connected in common to a horizontal word line WL. The input to each word line WL is fed by a row decoder 10, which serves to decode the row address based on the input address to the ROM device. In a similar manner, memory cells MC in the same column have the drains of their respective MOS transistor connected in common to a vertical bit line BL. Each of the bit lines BL is multiplexed via a multiplexer 12 to the input of a sense amplifier 14. A typical column decoder 16 includes and controls a multiplexer 12 consisting of a number of MOS transmitting transistors denoted MY.
When the conventional ROM device of FIG. 1 is accessed by external logic, an address comprising of a number of address bits is input to the row and column decoders 10 and 16 respectively for decoding. Based on the result of the decoding, a corresponding word line WL is enabled by the row decoder 10 to be the selected word line. Likewise, several corresponding bit lines BL will also be enabled by the column decoder 16 and multiplexed by multiplexer 12 into the sense amplifier 14 to be the selected bit lines. The number of the selected bit lines is determined by the number of I/O pins of the ROM IC device in question. The typical number of I/O pins found in commercial ROM IC's is eight, sometimes sixteen, corresponding to the byte- or word-accessed devices respectively. The intersections of the selected word line and the selected bit lines are the memory locations that correspond to the addressed memory location intended by the issued address.
Reference numeral 3 found in FIG. 1 generally shows the flow path of the current flowing through the circuit path comprising the selected memory cell MC, the transmitting transistor MY of the multiplexer 12, and the sense amplifier 14. This current flow path is also depicted in FIG. 2.
If a memory cell accessed in the process described above contains a null bit of information, that is, the bit is not programmed and the channel of the MOS transistor constituting the memory cell is not implanted during the programming phase of the ROM device fabrication, then the particular memory cell MC would remain to be a conducting component in the flow path diagram of FIG. 2. Such non-programmed memory cell will be referred to as an ON cell in the memory array of the ROM device. On the other hand, if the accessed memory cell is indeed programmed by implantation in the photo-masked programming phase, then the MOS transistor of the memory cell MC in the flow path diagram of FIG. 2 would be turned off. The MOS transistor in the memory cell MC would normally acquire a threshold voltage higher than the normal word line voltage can achieve. This allows a minor leakage current when the transistor remains in its off state. Similarly, such a memory cell having a turned-off transistor will be referred to as an OFF cell.
Sense amplifier 14 distinguishes between the ON and OFF cells as multiplexed thereto. The principle is to sense and distinguish between the scale of the current that flows in the path diagram of FIG. 2. With a ON cell, the current is detectably large while in the case of an OFF cell, the leakage current is too small to be detected by the sense amplifier 14. The output of the sense amplifier 14 is a voltage SAOUT that represents the sense result as either ON or OFF.
In a typical ROM device implementation, the sense amplifier 14 outputs an SAOUT voltage that is converted by the output stage 18 into a logical low voltage "0" when an ON cell is sensed. On the other hand, a logical high voltage "1" will be issued when an OFF cell is sensed. The output stage 18 of the sense amplifier 14 may comprise, for example, an OP buffer. However, depending on the implementation of the electrical system in the ROM IC device, logical voltages high and low may be generated to reflect the sense of the ON and OFF cell respectively.
FIG. 3 schematically shows a block diagram layout of the conventional flat-type ROM IC device. The flat-type ROM differs from the ROM device of FIG. 1 in that its rows of memory cells are arranged into banks. A defined number of rows of memory cells in the memory array are grouped together to form "banks". For the row decoder of the flat-type ROM device, in addition to the individual word lines WL connecting the gates of each transistor of the memory cells in a row, bank-selecting word lines BWL are also required to be enabled when the device is accessed.
Refer now to FIG. 4. For the column decoder, 2.sup.n (for example, 16, or 32, or more) memory cells MC in the same column are organized in a group and have the drains of their MOS transistors tied together to form a diffusion line. There is a similar arrangement for the sources of the respective MOS transistors in the same organized group of 2.sup.n memory cells MC in a column. The diffusion line formed by the connection of each of the drains in a group is also the source-connected diffusion line for the next consecutive group of memory cells. This can be observed in FIG. 4. A cascade of memory cell banks, in which each bank comprising the 2.sup.n rows, are thus formed to construct the entire memory array for the ROM device. FIG. 4 of the drawing shows the generally equivalent circuit of the memory array of the flat-type ROM IC of FIG. 3.
One end of each of the diffusion lines is connected to a bit line by a bank-selecting transistor BT, as shown in FIG. 4. Each of the diffusion lines that connects the drains or sources of the MOS transistors of the memory cells grouped together as a bank is referred to herein as local bit line LBL. There are thus a total of 2.sup.n memory cells gathered in every local bit line LBL. The entire bit line that connects the bank-selecting transistors BT in a column is referred to herein as the global bit line GBL. The bank-selecting transistor BT has a similar structural configuration as that of the memory cell MC. The gates of the bank-selecting transistors in the same row are also tied together as is the case of the word lines to form a bank-selecting word line BWL. Based on the design of the ROM device, there may be more than one bank-selecting transistor BT utilized to connect the local bit line LBL to the global bit line GBL.
With reference to FIGS. 3 and 4, when a ROM read access is intended, the row decoder 10 issues not only to enable the one or several word lines WL, there is one or several bank-selecting word lines BWL also enabled. Similarly, through the multiplexing of the multiplexer 12, one or several global bit lines GBL may be enabled as well by the column decoder 16. The selected global bit line GBL, which is the data bit line, has its one end connected to the input of the sense amplifier 14, and is connected to the local bit line LBL at its other end via the multiplexer 12 and the enabled bank-selecting transistor BT. The connection is then relayed via the memory cell MC that is enabled at the gate of its MOS transistor by the selected word line WL.
To constitute a complete electrical signal path for the reading of the memory content in the memory cell MC at the intersection of the selected word line and global bit line GBL, a return path must be provided. This is done by relaying the path through the local bit line LBL connected to the other of the source/drain pair of the MOS transistor of the memory cell MC, via the global bit line GBL connected thereto and back to the multiplexer 12 for connection to the system ground Vss for the completion of the path. This complete path is identified by the dashed line 3 in FIG. 4, and is further depicted in the flow path diagram of FIG. 5. Notice is made to the fact that both the two conventional ROM IC device constructions as outlined in FIGS. 1 and 3 require the use of a multiplexing means to fulfill the memory content reading operation of the ROM IC device. In the case of the flat-type ROM device of FIG. 3, the additional use of bank-selecting transistor is further required.
As is well known in the art, the fabrication of semiconductor devices normally involves a procedure including tens of complicated process steps. Any defect in any one of these steps almost inevitably leads to the result of a useless device. In the case of the ROM IC semiconductor devices, if the defects fall in the range of the bypassed sections, namely those memory locations that will never be accessed in the customer's particular application, then the device may still be considered useful. However, the standard testing procedure in most fabrications will still reject these devices as unacceptable, since all memory locations are thoroughly tested before the device can be qualified to ship. This practice leads directly to the reduction of the yield and the increase of cost.
Conventional techniques for the repair of such defective devices involve the use of extra-prepared, programmable memory cells based on the techniques such as PROM. This scheme of salvaging the otherwise would-be-wasted devices involves the sacrifices in device size, process complexity, testing overhead, as well as costs.